1. Field of the Invention
The present invention relates to a pulse amplitude modulation (hereinafter, "PAM") communication system, and more particularly, to an improved symbol timing recovery circuit for a PAM communication system.
2. Background of the Related Art
FIG. 1 illustrates a basic base band PAM communication system. The system includes a PAM unit 10 in a transmit terminal for modulating the pulse width of a binary data signal ak and outputting an analog signal s(t), an analog/digital converter (hereinafter, "ADC") 20 for converting an analog signal r(t) received from a channel CH into a digital signal rk and a symbol timing recovery (hereinafter, "STR") circuit 30 for receiving output signal rk of the ADC 20, and carrying out a timing error detection and correction and feeding back the corrected signal to the ADC 20. An equalizer 40 removes the noise components from output signal rk of the ADC 20 and a slicer 50 converts an output signal of equalizer 40 to a binary data signal ak.
At this time, the STR circuit 30 outputs a sampling signal either in accordance with signal r(t) applied to ADC 20 (feed forward method, as shown in dotted line) or in accordance with signal rk outputted from ADC 20 (feed back method). Here, the feed back method is employed to take advantage of digital signal processing capability.
FIG. 2 depicts a block diagram of a PAM communication system including a plurality of channels, each of the channels CH1, . . . , CHn basically includes a base band PAM communication system. A serial-to-parallel converter (hereinafter, "SPC") 60 and a parallel-to-serial converter (hereinafter, "PSC") 70 serve to integrate the respective channels CH1, . . . , CHn.
FIG. 3 shows a plurality of ADC-STR circuits in the system of FIG. 2. The ADC-STR circuits are identical to each other in structure and can be respectively broadly regarded as a phase locked loop (hereinafter, "PLL"). Here, the PLL operation principle is based on an algorithm of "Symbol Timing Recovery" disclosed in the article entitled "Timing Recovery in Digital Synchronous Data Receiver" by K. Mueller and M. Muller, IEEE. T.sub.-- COM, May 1996. The plurality of STRs 30-1, . . . , 30-n each respectively include a timing error detector (hereinafter, "TED") 11 for receiving a corresponding one of digital signals r.sup.1 k, . . . r.sup.n k outputted from ADCs 20-1, . . . , 20-n, and a voltage controlled oscillator (hereinafter, "VCO") 12 for being oscillated in accordance with a timing error signal outputted from TED 11 and outputting a sampling signal to a corresponding one of ADCs 20-1, . . . , 20-n.
The operation of the thusly constituted base band PAM communication system will now be described with reference to FIGS. 2 and 3. First, a transmit terminal Tx distributes binary data ak (k=0, 1, 2 . . . ) to the plurality of channels CH1, . . . , CHn through the SPC 60. The distributed binary data b.sup.1 k, . . . b.sup.n k are converted to analog signals s.sup.1 (t), . . . , s.sup.n (t) in PAM units 10-1, . . . , 10-n.
In a receive terminal Rx, the received signals r.sup.1 (t), . . . r.sup.n (t) are formed into digital signals r.sup.1 k, . . . r.sup.n k through the ADCs 20-1, . . . , 20-n. At this time, a sampling signal according to an exact timing is required in ADCs 20-1, . . . , 20-n. That is, as shown in FIG. 3, TEDs 11 respectively detect timing error signals from digital signals r.sup.1 k, . . . r.sup.n k outputted from ADCs 20-1, . . . , 20-n, and respectively, drive the VCOs 12 with voltages proportional to the detected timing error signal, whereby sampling signals respectively outputted from the VCOs 12 are respectively applied to ADCs 20-1, . . . , 20-n.
Each of the ADCs 20-1, . . . , 20-n carries out a sampling operation with regard to respective received digital signals r.sup.1 (k), . . . r.sup.n (k) and output respective digital signals r.sup.1 k, . . . r.sup.n k from which timing errors are removed. The equalizers 40-1, . . . , 40-n serve to restrain distortion or noise which has occurred in the channels. Binary digits b.sup.1 k, . . . b.sup.n k are respectively restored through the slicers 50-1, . . . , 50-n. Therefore, the binary digits b.sup.1 k, . . . b.sup.n k, which are processed independently at each channel and in parallel, are integrated in the PSC 70 and restored into a series of serial data ak which are finally outputted.
As described above, in the PAM communication system including a plurality of channels, an N plurality of VCOs 12 is required because the ADC-STR circuits are independently operated. Here, the N plurality of VCOs 12 is operated under an identical frequency so that it is impossible to avoid mutual interference, resulting in disabling a normal PLL operation. In addition, when an N plurality of receivers corresponding to an N plurality of channels is integrated in a single chip, the interference between the VCOs is further increased, thereby failing a normal timing recovery.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.